The present invention relates to a semiconductor device, and in particular, relates to a semiconductor device having static memory cells.
The present inventors have investigated the following techniques related to a semiconductor device having static memory cells.
In an SRAM (Static Random Access Memory) having a plurality of static memory cells arranged in a matrix, the selection terminals of the memory cells in the respective rows are coupled to the respective word lines, and the data input/output terminals of the memory cells in the respective columns are coupled to the respective complementary data lines (also referred to as complementary bit lines). The complementary data lines are common-coupled to a complementary common data line through a Y selection switch circuit including a plurality of column selection switches one-to-one coupled to the complementary data lines. In such an SRAM, a power supply voltage supplied to a memory cell array is maintained constant.
For example, Patent Documents 1 and 2 and Non-patent Document 1 describe techniques related to such a semiconductor device.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2005-108307
[Patent Document 2] Japanese Unexamined Patent Publication No. Hei 6(1994)-314491
[Non-patent Document 1] “A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Stabilizing Circuits” written by S. Obayashi et al., 2006 Symposium on VLSI Circuits Digest of Technical Papers